This invention relates generally to a electronic or semiconductor device package structure and a method of packaging an electronic or semiconductor device utilizing a film carrier.
The typical method of processing packaged integrated circuit semiconductor devices or IC chips involves the steps of securing a semiconductor chip to a die pad mounted on a lead frame, wire bonding the external electrodes of the semiconductor chip to the inner distal ends or terminals of the lead frame and molding the wire bonded components with a thermosetting resin, such as an epoxy resin, and lastly, cutting or severing the respective terminals after packaging.
In recent years, electronic devices have been miniaturized and decreased in overall thickness and the semiconductor devices and IC chips employed in these devices are provided with high packaged density. It is, therefore, desirable that a thin and miniaturized packaging of semiconductor devices be provided for use in such thinshaped electronic devices. An arrangement of the semiconductor device which meets such requirements is the placement of semiconductor IC chips in device receptacles formed in a film carrier and electrodes or bonding pads of the semiconductor IC chip are connected directly to bumps provided on lead fingers of the film carrier. The composite structure then undergoes encapsulation with a material, such as a liquidized resin, e.g., an epoxy resin, or other potting material completing the packaging process.
FIG. 3 is a plan view of a plurality of IC semiconductor devices 6, 6A, 6B, etc. secured relative to a film carrier 1 to assist in the foregoing explanation. Film carrier 1 (hereinafter referred to as "film") has a thickness in the range of about 50 .mu.m to 100 .mu.m and is formed with a series of device apertures 2, 2A, 2B, etc. at equal spacings in a longitudinal direction of film 1. Film apertures 2 each have an area larger than a surface area of semiconductor chips 6, 6A, 6B, etc. A plurality of fingers or finger contacts 3 are provided on film 1. Contacts 3 are made of a metal foil which exhibit, as is the case for copper, high electrical conductivity and are each about 30 .mu.m to 40 .mu.m in thickness and about 50 .mu.m to 300 .mu.m in width. A part of finger contacts 3 protrude or cantilever over and into apertures 2 forming free distal ends 3A. As shown in FIG. 4, the lower surfaces of finger ends 3A are formed at a predetermined angle and are provided with terminals or bumps 4 connected to corresponding bonding pads 6' of semiconductor chips 6. Film 1 also has sprocket holes 5 for transport of film 1 during processing.
FIG. 4 depicts an example of one means for mounting semiconductor chips 6 on film 1. Semiconductor chips 6 are loaded on a chip board 8 and chips 6 are arranged or set in a predetermined position by means of positioning guide 9. Film 1 is guided along a path by tape rail 10 in a vertical direction by means of a sprocket member (not shown) engaging sprocket holes 5 of film. Movement of film 1 is terminated when apertures 2 are in aligned relationship with semiconductor chips 6. This alignment is carried out via guide 9. Next, a precision alignment of the bonding pads 6' on semiconductor chip 6 and relative to finger contact ends 3A and bumps 4 is performed. During the occurrence of this alignment step, a heated bonding tool 11 is lowered to press the individual finger contact ends 3A of finger contacts 3 and bumps 4 are weld bonded to the bonding pads 6'. Next, as shown in FIG. 5, film 1 is moved through a molding station wherein semiconductor chips 6 and a portion of fingers 3 are encapsulated, for example, by molding, squeegee printing or potting, in a sealing resin material 7 comprising a liquid sealing resin, such as, an epoxy resin, containing a filler like silica and having a high viscosity. Then, fingers 3 and outer portions of film 1 are trimmed away forming a packaged semiconductor device D illustrated in FIG. 5.
As illustrated in FIG. 6, semiconductor device D is then mounted on a printed wiring board 20 functioning, for example, as an external circuit board and having formed on its upper surface a conductive lead pattern 21. Finger contacts 3 of chip 6 are then soldered to conductive pattern 21 and, thereafter, finger contacts 3 are sealed by means of a sealing resin 22 via squeegee printing or potting.
Thus, the prior art process for packaging semiconductor device D comprises alignment of semiconductor chips 6 relative to finger contact ends 3A on film 1, bonding bumps 4 of finger contact ends 3A of film 1 to bonding pads 6' provided on semiconductor chips 6, encapsulating semiconductor chips 6 and a portion of finger contacts 3 with a sealing resin material 7 and, thereafter, removing the outer portions of finger contacts 3 including portions of film 1.
When packaging semiconductor device D on printed wiring board 20, the sealing resin for sealing semiconductor chips 6 is required to have a high viscosity characteristics and contain a silica type filler in order to both increase its adherence quality to the encapsulated device D and reliability minimize differences in the linear coefficient of expansion between the encapsulated device D and printed wiring board 20. These exists, however, a high probability that the active surface of semiconductor chip 6 containing IC circuitry will be defaced or disordered by the encapsulating filler material. Furthermore, sealing resin material 7 is more than 200 .mu.m in thickness and it is not possible to reduce the thickness of this encapsulation to 100 .mu.m or below. Hence, semiconductor device D cannot be packaged unless finger contacts 3 are subjected to a forming process toward reducing the overall thickness of device D. This forming process involves the bending and reshaping of the outer extremities of finger contacts 3 to overcome the thickness of the molded package as depicted in FIG. 6. The forming process is quite difficult to perform, particularly compared with the use of a lead frame because finger contacts 3 are of very small thickness and very delicate to maneuver. Under such circumstances, problems arise wherein finger contacts 3 tend to be severed during the forming process or there is an increased possibility of misalignment or rearrangement of outer ends 3B of finger contacts 3 subjected to the forming process resulting in open electrical connections or poorly formed electrical connections when automated bonding contact of ends 3B to conductive pattern 21 is accomplished.
As depicted in FIG. 5, sealing resin material 7 is comparatively large in thickness. Thus, finger contacts 3 must undergo forming, which leads to the problem that a total thickness after packaging semiconductor device D becomes large resulting in an overall higher height dimension for the board which must be taken into consideration in the design of the size and overall dimensions of a housing for a compact, thin-shaped electronic device.
In addition, the linear coefficient of expansion of semiconductor chips 6 is approximately 3.5.times.10.sup.-6 while that of printed wiring board 20 is nearly 1.times.10.sup.-4. Although the linear coefficient of expansion of the sealing resin is reduced because of the incorporated filler, its linear coefficient of expansion approximates that of printed wiring board 20.
In performing a temperature cycle test, thermal stress is caused by a difference in the linear coefficient of expansion between semiconductor chips 6 and printed wiring board 20 and resultant effect of the stresses is concentrated on the external bonding portions between finger contacts 3 and conductive pattern 21. As a result, cracks are produced in finger contacts 3 or contacts become dislodged from pattern 21. Moreover, after package semiconductor device D is bonded on pattern 21 of board 20, semiconductor chip 6 itself varies in temperature due to electrical operation and, as a result the thermal stress created by the operating temperature of chips 6 within periods of no operation produces cracks in finger contacts or leads 3 some of which eventually become dislodged from pattern 21.
It is a primary object of this invention to obviate the foregoing problems inherent in the prior art process of semiconductor device packaging.
It is another object of this invention to provide a structure and a method of packaging a semiconductor device which provide the advantages that a semiconductor device can be face-down-packaged on a circuit board without the requirement of a reforming process for the finger contacts to which the bonding pads of a semiconductor chip are connected without deterioration due to cracks forming in the finger contacts due to thermal stress developed in subsequent operational use after packaging of the semiconductor device on the circuit board.